The present invention relates to a semiconductor device. Specifically, the invention relates to a semiconductor device for outputting a reference voltage.
According to the prior art, a reference voltage circuit is used for feeding a reference voltage to all the control circuits in an integrated circuit (hereinafter referred to as an “IC”). Therefore, the reference voltage circuit is required to always output a certain voltage not adversely affected by temperature variations nor by power supply voltage variations. FIG. 6 is a cross sectional view of a semiconductor device that constitutes a conventional MOS reference voltage circuit. The semiconductor device shown in FIG. 6 is manufactured employing p-type substrate 1. In the surface portion of p-type substrate 1, p-type well layer 73 is formed. Depletion-type MOSFET 101 and enhancement-type MOSFET 102 are formed in the surface portion of p-type well player 73. Depletion-type MOSFET 101 and enhancement-type MOSFET 102 are spaced apart from each other by field oxide film 17 (See, for example, Unexamined Laid Open Japanese Patent Application Publication No. 2003-31678).
In depletion-type MOSFET 101, n+-type drain layer 5 and n+-type source layer 6 are formed in a first surface portion of p-type well player 73 such that n+-type drain layer 5 and n+-type source layer 6 are spaced apart from each other. In the first surface portion of p-type well player 73, n−-type depletion layer 7 is formed such that n−-type depletion layer 7 is in contact with n+-type drain layer 5 and n+-type source layer 6. Gate electrode 10 is formed above n−-type depletion layer 7 with gate oxide film 9 interposed between n−-type depletion layer 7 and gate electrode 10.
In enhancement-type MOSFET 102, n+-type drain layer 11 and n+-type source layer 12 are formed in a second surface portion of p-type well player 73 such that n+-type drain layer 11 and n+-type source layer 12 are spaced apart from each other. In the second surface portion of p-type well player 73, p-type channel layer 13 is formed such that p-type channel layer 13 is in contact with n+-type drain layer 11 and n+-type source layer 12. Gate electrode 16 is formed above p-type channel layer 13 with gate oxide film 15 interposed between p-type channel layer 13 and gate electrode 16. In a third surface portion of p-type well player 73, p+-type pickup layer 74 is formed. Pickup layer 74 is spaced apart from enhancement-type MOSFET 102 by field oxide film 19.
High-potential power supply terminal Vcc is connected electrically to n+-type drain layer 5 in depletion-type MOSFET 101. Output terminal Vref that outputs a reference voltage is connected electrically to n+-type source layer 6 and gate electrode 10 in depletion-type MOSFET 101 and to n+-type drain layer 11 and gate electrode 16 in enhancement-type MOSFET 102. Ground terminal GND is connected electrically to n+-type source layer 12 in enhancement-type MOSFET 102 and p+-type pickup layer 74. The MOS reference voltage circuit as described above makes it possible to detect the cell voltage of a lithium ion battery including, for example, one battery cell very precisely.
Now the configuration of a voltage detecting circuit, which employs the conventional semiconductor device for a MOS reference voltage circuit, will be described below. FIG. 7 is a block circuit diagram describing the configuration of a voltage detecting circuit that uses the conventional semiconductor device for the MOS reference voltage circuit thereof. In FIG. 7, voltage detecting circuit 110 includes high resistance R1, resistance R2, and voltage detecting circuit section 112. Voltage detecting circuit section 112 includes comparator 114 and MOS reference voltage circuit 113. The reference voltage outputted from MOS reference voltage circuit 113 is applied to the reference voltage side of comparator 114. The voltage obtained by dividing the output voltage from a lithium ion battery, including lithium battery cells 111 connected in series, with resistance R1 and resistance R2 is applied to the input potential side of comparator 114.
As described above, a high voltage is divided by resistance to a lower voltage and the lower voltage is compared with a reference voltage to detect the high voltage. Alternatively, a high voltage is divided by a differential amplifier circuit to a lower voltage and the lower voltage is compared with a reference voltage to detect the high voltage.
However, a large voltage difference is caused between a battery voltage and a reference voltage level, to which the battery voltage is lowered, in the voltage detecting circuit section in a charging control IC for a battery including many cells. The large voltage difference makes it hard to detect the battery voltage with high precision. Since only one reference voltage circuit is included, it is impossible to detect the voltage of every cell.
In view of the foregoing, it would be desirable to obviate the problem described above, and to provide a semiconductor device that facilitates outputting a reference voltage for an arbitrary potential. It would further be desirable to provide a semiconductor device that facilitates detecting the voltage of every cell in the battery with high precision.